A Parallel Algorithm for Hierarchical Circuit Extraction

Parallel Performance of Hierarchical Multipole Algorithms for Inductance Extraction

Parasitic extraction techniques are used to estimate signal delay in VLSI chips. Inductance extraction is a critical component of the parasitic extraction process in which on-chip inductive effects are estimated with high accuracy. In earlier work [1], we described a parallel software package for inductance extraction called ParIS, which uses a novel preconditioned iterative method to solve the...

Parallel Algorithms for Cad with Applications to Circuit Extraction By

Parallel algorithms for VLSI circuit extraction

Parallel processing has recently become an extremely attractive and cost effective way of achieving orders of magnitude performance improvements in VLSI CAD applications. In this paper, we propose parallel algorithms to speed up the VLSI circuit extraction task. Given a VLSI layout as input, the problem of circuit extraction consists of determining the circuit connectivity and estimating the va...

PACE2: an improved parallel VLSI extractor with parameter extraction

In ICCAD88, we had proposed an efficient parallel algorithm PACE to speed up the first phase of VLSI circuit extraction, called the net list extraction phase. In this paper, we describe an algorithm PACE2 targeted to the second phase of extraction, called the parameter extraction phase. We have interfaced two models for resistance and capacitance. In this paper, we also propose a different part...

Parallel iterative methods for dense linear systems in inductance extraction

Accurate estimation of the inductive coupling between interconnect segments of a VLSI circuit is critical to the design of high-end microprocessors. This paper presents a class of parallel iterative methods for solving the linear systems of equations that arise in the inductance extraction process. The coefficient matrices are made up of dense and sparse submatrices where the dense structure is...